1. Technical Field of the Invention
The present invention relates to the field of failure analysis, and more particularly, to the analysis of failures in a sample, such as a wafer or a die sliced from the wafer.
2. Description of Related Art
The manufacturers of semiconductor devices, whether these devices are still in wafer form or package form, will normally test the semiconductor devices before their shipment. The vast majority of these tests are electrical in nature. Occasionally, some of the devices will fail the testing procedures. It is also possible that a device fails tests performed by a customer before or after installation in a product. These failing circuits are then shipped back to the manufacturer for failure analysis. It is important for the manufacturer to understand the cause of the failures in order to improve the yield of the devices.
The failures are separated into two main categories, either functional failures or DC failures. The functional failures occur when a sample does not respond properly to generated functions that are applied to the circuit. The DC failures are identified by the presence of shorts, leakage current, etc. in response to imposed test conditions.
In order to determine the cause of a failure, the possible areas where failures are caused in the circuit need to be identified. Hence, steps are performed to identify "hot spots" in the sample. These steps include, for instance, the use of an emission microscope that detects heat, or the coating of the sample with liquid crystal. With either of these methods, the test conditions at which the sample failed are again applied to the sample and the hot spots are noted and recorded. For example, the sample and its hot spots may be photographed to provide a visual record of the hot spot locations. After the hot spots are identified in the photograph, the integrated circuit is then scanned by a scanning electron microscope, or is optically inspected using an optical microscope. This inspection is done in order to detect any obvious defects prior to performing reverse engineering.
When the initial inspection of the sample under the scanning electron microscope or optical microscope does not reveal any obvious defects, reverse engineering is performed in order to strip back the sample layer by layer. The stripping may be done either by a dry etch technique, such as reactive ion etching, or a wet etch technique. After each layer has been stripped, the sample (the integrated circuit package or wafer) is returned to the scanning electron microscope or optical microscope and once again inspected for defects. A defect is normally recognized by either a particle or a hole or some type of broken metal in the sample. The cause of the failure of the sample will thus be identified.
One of the problems of this known method for analyzing the failures of a sample is the requirement that entire layers be stripped from the sample prior to re-inspection under the scanning electron microscope or optical microscope. This is due to the fact that when scanning with a scanning electron microscope, only the surface layers are visible so that stripping by surface layers is required to reveal defects.